The present invention relates generally to semiconductor device manufacturing and, more particularly, to a method for image reversal of implant resist using a single photolithography exposure and structures formed thereby.
The manufacturing of semiconductor devices is dependent upon the accurate replication of computer aided design (CAD) generated patterns onto the surface of a device substrate. The replication process is typically performed using lithographic processes, followed by a variety of subtractive (etch) and additive (deposition) processes. More particularly, a photolithography process typically includes applying a layer of a photoresist material (i.e., a material that will react when exposed to light), and then selectively exposing portions of the photoresist to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.), thereby changing the solubility of portions of the material. The resist is then developed by washing it with a basic developer solution, such as tetramethylammonium hydroxide (TMAH), thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer.
In the fabrication of complementary metal oxide semiconductor (CMOS) devices, several implant masks are used to form appropriate source and drain areas on the chip. For p-type and n-type CMOS devices NFETs, PFETs), some of these patterns are complementary; that is, the pattern used for creating the p-type devices is the reverse of the pattern used for creating the n-type devices. More specifically, two separate masks are used in CMOS device processing in which either a positive or negative resist is used to carry out two separate, complementary masking and implanting steps. For example, a first implant pattern is formed by creating a first patterned (positive or negative) photoresist layer over a substrate. A first ion implantation is used to implant the exposed areas of the substrate with a first dopant material (e.g., a p-type material). Subsequently, the first patterned layer is stripped and a second pattered resist (of the same tone as the first resist) is used to expose the complementary regions of the substrate regions in order to carry out the complementary implantation with a second dopant material (e.g., an n-type material).
However, as devices become even more miniaturized over time, the conventional methods for complementary device implantation are more susceptible to alignment errors as a result of the separate masking steps. Such alignment errors would limit the density and performance of the resulting devices. These alignment errors may include rotation errors, translation errors, overlap errors, and/or image size deviations. In turn, the possibility of incurring one or more of these errors results in the increase of the overall device error placement budget, thereby reducing valuable chip real estate that would otherwise be used for additional devices.
An image reversal process is another known technique used in CMOS device processing, in which a combination of positive and negative resists is used for such steps as gate/line patterning or contact hole patterning. In one approach, a positive photoresist layer formed over a substrate is patterned to create an opening for a gate pattern or a line pattern. Subsequently, a negative resist is formed over the irradiated positive photoresist, including the formed opening. Then, the negative resist is recessed such that it remains only in the area defined by the opening formed in the positive resist layer, while the remaining positive resist is removed. The remaining hardened negative resist defines the location for the gate or line pattern.
Although this type of image reversal process may be used to form certain types of semiconductor structures, it is not particularly suited for the type of complementary implant regions discussed above, due to intermixing between negative and positive photoresists during apply. The intermixing will cause deformation of the underlying first resist pattern, impacting line width control and causing residual resist defects. Moreover, even if this approach were able to be adapted for complementary device implantation, there are still two separate lithography steps needed in accomplishing the image reversal.
Another existing approach is to utilize spun-on glass (SOG) over photoresist for image reversal purposes. However, SOG is an oxide material that is typically removed using harsh solvents such as dilute HF or buffered HF, and which in turn tends to cause damage to the other oxide layers on the device substrate.
Unfortunately, a significant part of the cost of an integrated circuit chip is contained in the lithography processes used to pattern these implant mask levels. As such, it would be desirable to be able to implement image reversing for applications such as CMOS device implantation, but without the added lithography step used heretofore (or the added risk of device damage in removing SOG) to accomplish the image reversal.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for image reversal in semiconductor processing. In an exemplary embodiment, the method includes forming a first implant mask layer upon a semiconductor substrate and forming a patterned photoresist layer over the first implant mask layer. Portions of the first implant mask layer not covered by the patterned photoresist layer are removed so as to expose non-patterned portions of the substrate. The photoresist layer is then removed, and a second implant mask layer is formed over the non-patterned portions of the substrate, wherein the first implant mask layer has an etch selectivity with respect to the second implant mask layer. The remaining portions of the first implant mask layer are removed to expose a reverse image of the substrate, including initially patterned portions of the substrate.
In another aspect, a method for implementing image reversal for semiconductor device implantation includes forming a first implant mask layer upon a semiconductor substrate and forming a patterned photoresist layer over the first implant mask. Portions of the first implant mask layer not covered by the patterned photoresist layer are removed so as to expose non-pattered portions of the substrate. The photoresist layer is removed, and the exposed, non-pattered portions of the substrate are subjected to a first implantation. A second implant mask layer is then formed over the non-patterned portions of the substrate, wherein the first implant mask layer has an etch selectivity with respect to the second implant mask layer. The remaining portions of the first implant mask layer are removed to expose a reverse image of the substrate, including initially patterned portions of the substrate. The exposed initially patterned portions of the substrate are then subjected to a second implantation.
In still another aspect, a semiconductor device has a first implant region having a first conductivity type and a second implant region having a second conductivity type, wherein the first and said second implant regions are self-aligned with respect to one another.